1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it relates to a method of forming a work pattern including resist pattern formation utilized for manufacturing a semiconductor integrated circuit device, particularly a resist pattern forming step effective for obtaining high dimensional accuracy and alignment accuracy of a wiring pattern or the like having a line width of not more than 0.20 xcexcm.
2. Description of the Background Art
When manufacturing a semiconductor integrated circuit (semiconductor device) at present, selective working is performed on an underlayer such as a semiconductor substrate through etching or ion implantation. In this case, a pattern of a composition sensitized by active rays such as ultraviolet rays, X-rays or electron rays, i.e., the so-called photosensitive resist coating (hereinafter simply referred to as xe2x80x9cresist filmxe2x80x9d) is formed on the underlayer, in order to selectively protect a worked portion of the underlayer.
The most generally employed method of forming a resist pattern is carried out through application of ultraviolet rays employing a stepping projection aligner (stepper) having a light source of a mercury lamp for g rays (wavelength: 436 nm) or i rays (wavelength: 365 nm), a KrF excimer laser (wavelength: 248 nm) or an ArF excimer laser (wavelength: 193 nm).
A photomask is mounted on the stepper for performing exposure, while the photomask, referred to as a reticle, obtained by forming a circuit pattern on a glass substrate with a shielding film of chromium (Cr) or the like must be precisely aligned (overlaid) for correctly setting positional relation between the photomask and a circuit pattern already formed on the substrate.
The pattern drawn on the photomask is contracted through a lens and transferred to the resist film applied to the semiconductor substrate. Thereafter the resist film is developed thereby enabling formation of a resist pattern.
It is assumed that this resist pattern forming step must be repeated by about 20 to 30 times in general, in order to manufacture a semiconductor integrated circuit device.
The degree of integration and the performance of a semiconductor integrated circuit are increasingly improved in recent years, followed by requirement for further refinement of a circuit pattern. In relation to a DRAM (dynamic random access memory), for example, a resist pattern having a line width of 0.20 to 0.18 xcexcm is drawn on a 64-Mbit DRAM subjected to mass production at present, and a KrF excimer laser beam (xcex=248 nm) is most generally utilized in a photolithography step therefore among ultraviolet rays. Further refinement of the pattern as well as improvement of dimensional accuracy and alignment accuracy are required for the future.
While a work pattern such as a wiring pattern is obtained by etching an underlayer film through a mask of a resist pattern, it has recently been recognized that there is such space width dependency (pattern density dependency) in formation of the work pattern that a critical dimension shift (the quantity of displacement from a resist pattern) resulting from dry etching varies with the space width of a region adjacent to the work pattern.
In other words, it has been recognized that the critical dimension shift on a rough region having a relatively large space width differs from that on a dense region having a relatively small space width on the work pattern. The difference between the critical dimension shift on the rough region having a relatively large space width and that on the dense region having a relatively small space width is hereinafter referred to as xe2x80x9ccritical dimension shift density differencexe2x80x9d.
This means that the dimensional accuracy of the work pattern is deteriorated in etching due to the space width dependency, while the critical dimension shift density difference is reaching an unignorable level following pattern refinement.
In particular, it is also recognized that large critical dimension shift density difference results from etching of a silicon oxide film or a silicon nitride film. However, the pitch of wires and the space between the wires and contact holes are increasingly narrowed due to the refinement and densification of the pattern and a self-aligned contact hole structure is generally employed. Therefore, a device structure obtained by stacking an insulator film such as a silicon oxide film or a silicon nitride film on a metal wiring film is requisite also in a gate forming step.
Therefore, a method of suppressing critical dimension shift density difference resulting from etching of the insulator film is necessary.
FIGS. 48 to 51 are sectional views showing an exemplary conventional wiring pattern forming method. The conventional wiring pattern forming method is now described with reference to FIGS. 48 to 51.
First, a polysilicon layer 2 is formed on a silicon substrate 1 in a thickness of 50 nm (500 xc3x85), then a silicon nitride film 3 is formed in a thickness of 165 nm (1650 xc3x85), and thereafter a photoresist film 4 is applied and prebaked at 100xc2x0 C. for 90 seconds, as shown in FIG. 48. At this time, the revolution speed in application is so adjusted that the thickness of the photoresist film 4 is 585 nm (5850 xc3x85).
Then, exposure is performed with a stepper having a KrF excimer laser (wavelength: 248 nm) 6 as a light source through a reticle (photomask) 5 on which wiring patterns are drawn at various pitches, as shown in FIG. 49. Off-axis illumination employing a ⅔ annular illumination aperture is applied under an illumination condition of NA (numerical aperture) =0.55.
Then, post-exposure baking (PEB) is performed at 110xc2x0 C. for 90 seconds and thereafter development is performed for 60 seconds with an aqueous solution of 2.38 percent by weight of tetramethylammonium hydroxide (TMAH), thereby obtaining a resist pattern 4a responsive to the reticle 5 as shown in FIG. 50.
Then, the resist pattern 4a is employed as a mask for etching the nitride film 3 and the polysilicon layer 2 through a parallel plate reactive ion etcher performing RIE (reactive ion etching) with a gas mixture of trifluoromethane (CHF3), tetrafluoromethane (CF4), argon (Ar) and oxygen (O2), thereby obtaining a wiring pattern (polysilicon pattern 2a and silicon nitride pattern 3a) as shown in FIG. 51.
FIG. 52 is a graph showing results of comparison of pattern sizes of the resist pattern 4a and a work pattern (multilayer structure of the polysilicon layer 2 and the silicon nitride film 3) obtained after etching. FIG. 52 plots the sizes (Line Width) of the resist pattern 4a and the work pattern subjected to etching, with reference to a line width of 0.24 xcexcm, with respect to space widths (Space) respectively.
FIG. 53 is a graph showing space width dependency based on FIG. 52. This graph shows dependency of critical dimension shift (CD (critical dimension) Shift) in etching at the line width of 0.24 xcexcm shown in FIG. 52 on the space width of an adjacent region. Referring to FIG. 53, critical dimension shift density difference xcex94 CD0 indicating the difference between critical dimension shifts of a densest pattern region and an isolated line pattern region having a sufficiently wide space is about 0.141 xcexcm.
As shown in FIG. 53, the critical dimension shift of a line pattern under rough environment is so large that sizing is necessary for narrowing a mask size from an original design size, in order to finish the isolated line pattern in response to the design. However, process tolerance such as exposure tolerance or focus tolerance (DOF: depth of focus) is narrowed as the mask size and the obtained resist pattern size are reduced, and hence it is undesirable that critical dimension shift density difference resulting from etching is large.
Therefore, it is important to suppress the critical dimension shift in dry etching, particularly space width dependency (pattern density dependency) of the critical dimension shift, i.e., critical dimension shift density difference.
When forming a resist pattern on an underlayer film of tungsten or aluminum having large grains on its surface following pattern refinement, deterioration of pattern dimensional accuracy is caused due to influence by halation from the grains. Also in relation to alignment in exposure, accuracy is similarly deteriorated due to the influence by the grains.
According to a first aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) forming an etching object on a semiconductor substrate, (b) forming a first resist film on the etching object, (c) patterning the first resist film to obtain a first resist pattern, (d) performing ion implantation into the first resist pattern, the thickness of the first resist pattern contracting by the ion implantation in the step (d), and (e) executing predetermined etching on the etching object using the first resist pattern as a mask to obtain a work pattern after execution of the steps (c) and (d), and the thickness of the first resist pattern after execution of the step (d) is set to a level satisfying such a condition that difference in critical dimension shift in the work pattern with respect to the first resist pattern caused between a dense pattern portion and a rough pattern portion in the work pattern is not more than a predetermined reference value and causes no hindrance to the predetermined etching.
In the method of manufacturing a semiconductor device according to the first aspect, as hereinabove described, the step (d) is so executed as to set the thickness of the first resist pattern to a level satisfying the condition that difference in critical dimension shift in the work pattern with respect to the first resist pattern caused between a dense pattern portion and a rough pattern portion in the work pattern is not more than the predetermined reference value and causes no hindrance to the predetermined etching, whereby the work pattern can be obtained with excellent dimensional accuracy through the step (e) also when the etching object is an insulating material and the work pattern has relatively large density difference.
Further, the first resist pattern is subjected to ion implantation through the processing in the step (d) to be improved in resistance against the predetermined etching, not to exert bad influence on the predetermined etching also when the thickness of the first resist pattern is reduced.
In addition, ion implantation is performed on the first resist pattern through the processing in the step (d) for relaxing roughness on an edge portion of the first resist pattern, whereby the first resist pattern can attain excellent linearity.
According to a second aspect of the present invention, the etching object includes an actual etching object and an ion prevention film, the step (a) includes steps of (a-1) forming the actual etching object on the semiconductor substrate and (a-2) forming the ion prevention film on the actual etching object, the ion implantation in the step (d) includes ion implantation from above the first resist pattern, and the ion prevention film prevents ions implanted in the step (d) from being implanted into the actual etching object.
In the method of manufacturing a semiconductor device according to the second aspect, the ion prevention film prevents the ions implanted in the step (d) from being implanted into the actual etching object, not to exert bad influence on the actual etching object by the ion implantation.
According to a third aspect of the present invention, the ion prevention film includes a silicon nitride film or a silicon oxynitride film, and the step (a-2) includes a step of forming the ion prevention film by plasma CVD.
In the method of manufacturing a semiconductor device according to the third aspect, the silicon nitride film or the silicon oxynitride film can be formed in a uniform thickness due to plasma CVD, not to exert bad influence on the shape of the first resist pattern.
According to a fourth aspect of the present invention, the ion prevention film includes an organic antireflection coating.
In the method of manufacturing a semiconductor device according to the fourth aspect, the ion prevention film includes the organic antireflection coating whose thickness contracts to reduce a step through ion implantation, whereby a step of the etching object can be flattened as compared with that before ion implantation and dimensional ununiformity of the work pattern caused by the step in the predetermined etching can be reduced.
According to a fifth aspect of the present invention, the step (a) further includes a step (a-3) of performing ion implantation into the organic antireflection coating forming the ion prevention film.
In the method of manufacturing a semiconductor device according to the fifth aspect, the step of the etching object can be remarkably flattened due to the ion implantation performed when carrying out the step (a-3) in addition to the step (d), whereby dimensional ununiformity of the work pattern caused by the step in the predetermined etching can be further reduced.
According to a sixth aspect of the present invention, the etching object includes first and second work areas, the first resist pattern includes a pattern for an etching mask for the first work area, the method further includes steps of (f) forming a second resist film at least on the second work area after execution of the step (d) and (g) patterning the second resist film to obtain a second resist pattern for an etching mask for the second work area, and the step (e) includes a step of executing the predetermined etching using the second resist pattern as a mask in addition to the first resist pattern.
In the method of manufacturing a semiconductor device according to the sixth aspect, a work pattern varied in line width difference can be obtained with excellent accuracy by executing the predetermined etching through the masks of the first resist pattern utilizing pattern contraction resulting from ion implantation and the second resist pattern not utilizing pattern contraction resulting from ion implantation.
According to a seventh aspect of the present invention, the step (f) includes a step of forming the second resist film on the overall surface of the etching object including the first pattern, and the first resist pattern is not substantially removed in execution of the step (g) due to composition change resulting from the ion implantation in the step (d).
In the method of manufacturing a semiconductor device according to the seventh aspect, the first resist pattern is not substantially removed in execution of the step (g) due to the composition change resulting from the ion implantation in the step (d), whereby formation of the second resist film in the step (f) can be executed through simplest full formation.
According to an eighth aspect of the present invention, the ion implantation in the step (d) includes ion implantation performed obliquely from above with respect to a vertical line a surface formed with the first resist pattern.
In the method of manufacturing a semiconductor device according to the eight aspect, the ion implantation in the step (d) is performed obliquely from above with respect to the vertical line on the surface formed with the first resist pattern for preventing ion implantation into the etching object also by side surfaces of the first resist pattern, so that ions are hardly implanted into the etching object under the first resist pattern. Thus, the etching object can be prevented from inconvenient ion implantation.
According to a ninth aspect of the present invention, the etching object has asperities on its surface, and the method further comprises a step (h) of performing ion implantation into the etching object before executing the step (b).
In the method of manufacturing a semiconductor device according to the ninth aspect, the asperities on the surface of the etching object is relaxed by the ion implantation in the step (d), whereby bad influence exerted by the asperities can be suppressed.
According to a tenth aspect of the present invention, the step (b) includes a step of performing exposure on the first resist film through a reticle of a predetermined pattern and thereafter executing development thereby obtaining the first resist pattern.
In the method of manufacturing a semiconductor device according to the tenth aspect, the asperities on the surface of the etching object is relaxed by the ion implantation in the step (d), whereby bad influence exerted by reflection from the asperities through the exposure in the step (b) can be suppressed.
According to an eleventh aspect of the present invention, the etching object has a mark for mask alignment on its surface.
In the method of manufacturing a semiconductor device according to the eleventh aspect, the etching object has the mark for mask alignment on its surface. While measuring accuracy of this mark is deteriorated due to the asperities on the surface, the asperities is relaxed by the ion implantation in the step (h) and hence the mask alignment accuracy can be improved following improvement in the measuring accuracy of the mark.
According to a twelfth aspect of the present invention, the step (h) includes steps of (h-1) forming a third resist film on the etching object, (h-2) patterning the third resist film to obtain a third resist pattern, the third resist pattern having an opening on a mark forming region including the mark, and (h-3) performing ion implantation into the mark forming region of the etching object using the third resist pattern as a mask.
In the method of manufacturing a semiconductor device according to the twelfth aspect, ions are implanted into the mark forming region of the etching object through the mask of the third resist pattern in the step (h-3) and the asperities on the surface of the mark forming region is relaxed due to the ion implantation in the step (h), whereby mask alignment accuracy can be improved following improvement in measuring accuracy of the mark.
Further, the third resist pattern can reliably prevent ion implantation into the etching object other than the mark forming region.
According to a thirteenth aspect of the present invention, the ion implantation in the step (d) includes a plurality of partial ion implantation operations different in implantation energy from each other.
In the method of manufacturing a semiconductor device according to the thirteenth aspect, a plurality of partial ion implantation operations different in implantation energy from each other are so performed as to homogeneously harden the first resist pattern along the thickness, whereby the predetermined etching in the step (e) can be executed without damaging the first resist pattern.
According to a fourteenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) forming an etching object on a semiconductor substrate, (b) forming a first resist film on the etching object, (c) patterning the first resist film to obtain a first resist pattern, (d) performing chemical reaction acceleration for accelerating decomposition on the first resist pattern, (e) performing curing including one of ion implantation, electron beam irradiation and ultraviolet irradiation on the first resist pattern, the thickness of the first resist pattern contracting by the curing in the step (e), and (f) executing predetermined etching on the etching object using the first resist pattern as a mask to obtain a work pattern after execution of the steps (c) to (e).
In the method of manufacturing a semiconductor device according to the fourteenth aspect, the first resist pattern contracts in thickness due to the curing executed in the step (e), whereby the work pattern can be obtained in excellent dimensional accuracy through the step (f).
In addition, decomposition of the first resist pattern is accelerated due to the chemical reaction acceleration in the step (d), whereby inconvenience resulting from generation of gas in the first resist pattern can be reliably avoided in execution of the step (f).
According to a fifteenth aspect of the present invention, the etching object includes first and second work areas, the first resist pattern includes a pattern for an etching mask for the first work area, the method further includes steps of (g) forming a second resist film at least on the second work area after execution of the step (e) and (h) patterning the second resist film to obtain a second resist pattern for an etching mask for the second work area, and the step (f) includes a step of executing the predetermined etching using the second resist pattern as a mask in addition to the first resist pattern.
In the method of manufacturing a semiconductor device according to the fifteenth aspect, work patterns different in line width from each other can be precisely obtained by executing predetermined etching through the masks of the first resist pattern utilizing contraction of the thickness and the pattern dimension resulting from curing and the second resist pattern not utilizing contraction of the thickness and the pattern dimension resulting from curing.
According to a sixteenth aspect of the present invention, the method of manufacturing a semiconductor device further comprises steps of (i) performing chemical reaction acceleration for accelerating decomposition at least on the second resist pattern before the step (f) and after the step (h), and (j) performing the curing at least on the second resist pattern before the step (f) and after the step (h).
In the method of manufacturing a semiconductor device according to the sixteenth aspect, etching resistance of the second resist pattern against the predetermined etching can be improved by the curing in the step (j). When the curing in the step (j) is so performed as to hardly contract the thickness of the second resist pattern, the pattern dimension of the second resist pattern can be maintained.
In addition, decomposition of the first and second resist patterns is accelerated due to the chemical reaction acceleration in the steps (d) and (i), whereby inconvenience caused by generation of gas in the first and second resist patterns can be reliably avoided in execution of the step (f).
According to a seventeenth aspect of the present invention, the chemical reaction acceleration includes at least either exposure or heat treatment on the etching object.
In the method of manufacturing a semiconductor device according to the seventeenth aspect, decomposition in the first or second resist pattern can be accelerated by performing exposure and heat treatment on the first or second resist pattern employed as the object.
According to an eighteenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of (a) forming an etching object having first and second work areas on a semiconductor substrate, (b) forming a first resist film on the etching object, (c) patterning the first resist film to obtain a first resist pattern on the first work area, (d) performing curing including one of ion implantation, electron beam irradiation and ultraviolet irradiation on the first resist pattern, the thickness of the first resist pattern contacting by the curing in the step (d), (e) forming a second resist film at least on the second work area after execution of the step (d), (f) patterning the second resist film to obtain a second resist pattern for an etching mask for the second work area and (g) executing predetermined etching on the etching object using the first and second resist patterns as masks to obtain a work pattern.
In the method of manufacturing a semiconductor device according to the eighteenth aspect, work patterns different in line width from each other can be precisely obtained by executing the predetermined etching through the masks of the first resist pattern utilizing contraction of the thickness and the pattern dimension resulting from the curing in the step (d) and the second resist pattern not utilizing contraction of the thickness and the pattern dimension resulting from the curing.
An object of the present invention is to provide a method of manufacturing a semiconductor device capable of suppressing critical dimension shift density difference in etching without hindering the etching.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.